initial commit, 4.5 stable
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This commit is contained in:
182
thirdparty/libtheora/x86/x86cpu.c
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182
thirdparty/libtheora/x86/x86cpu.c
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/********************************************************************
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* *
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* THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE. *
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* USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
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* GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
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* IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
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* *
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* THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2009 *
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* by the Xiph.Org Foundation and contributors *
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* https://www.xiph.org/ *
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* *
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********************************************************************
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CPU capability detection for x86 processors.
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Originally written by Rudolf Marek.
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function:
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********************************************************************/
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#include "x86cpu.h"
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#if !defined(OC_X86_ASM)
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ogg_uint32_t oc_cpu_flags_get(void){
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return 0;
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}
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#else
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# if defined(__amd64__)||defined(__x86_64__)
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/*On x86-64, gcc seems to be able to figure out how to save %rbx for us when
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compiling with -fPIC.*/
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# define cpuid(_op,_eax,_ebx,_ecx,_edx) \
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__asm__ __volatile__( \
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"cpuid\n\t" \
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:[eax]"=a"(_eax),[ebx]"=b"(_ebx),[ecx]"=c"(_ecx),[edx]"=d"(_edx) \
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:"a"(_op) \
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:"cc" \
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)
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# else
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/*On x86-32, not so much.*/
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# define cpuid(_op,_eax,_ebx,_ecx,_edx) \
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__asm__ __volatile__( \
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"xchgl %%ebx,%[ebx]\n\t" \
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"cpuid\n\t" \
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"xchgl %%ebx,%[ebx]\n\t" \
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:[eax]"=a"(_eax),[ebx]"=r"(_ebx),[ecx]"=c"(_ecx),[edx]"=d"(_edx) \
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:"a"(_op) \
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:"cc" \
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)
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# endif
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static ogg_uint32_t oc_parse_intel_flags(ogg_uint32_t _edx,ogg_uint32_t _ecx){
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ogg_uint32_t flags;
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/*If there isn't even MMX, give up.*/
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if(!(_edx&0x00800000))return 0;
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flags=OC_CPU_X86_MMX;
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if(_edx&0x02000000)flags|=OC_CPU_X86_MMXEXT|OC_CPU_X86_SSE;
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if(_edx&0x04000000)flags|=OC_CPU_X86_SSE2;
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if(_ecx&0x00000001)flags|=OC_CPU_X86_PNI;
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if(_ecx&0x00000100)flags|=OC_CPU_X86_SSSE3;
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if(_ecx&0x00080000)flags|=OC_CPU_X86_SSE4_1;
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if(_ecx&0x00100000)flags|=OC_CPU_X86_SSE4_2;
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return flags;
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}
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static ogg_uint32_t oc_parse_amd_flags(ogg_uint32_t _edx,ogg_uint32_t _ecx){
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ogg_uint32_t flags;
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/*If there isn't even MMX, give up.*/
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if(!(_edx&0x00800000))return 0;
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flags=OC_CPU_X86_MMX;
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if(_edx&0x00400000)flags|=OC_CPU_X86_MMXEXT;
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if(_edx&0x80000000)flags|=OC_CPU_X86_3DNOW;
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if(_edx&0x40000000)flags|=OC_CPU_X86_3DNOWEXT;
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if(_ecx&0x00000040)flags|=OC_CPU_X86_SSE4A;
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if(_ecx&0x00000800)flags|=OC_CPU_X86_SSE5;
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return flags;
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}
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ogg_uint32_t oc_cpu_flags_get(void){
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ogg_uint32_t flags;
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ogg_uint32_t eax;
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ogg_uint32_t ebx;
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ogg_uint32_t ecx;
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ogg_uint32_t edx;
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# if !defined(__amd64__)&&!defined(__x86_64__)
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/*Not all x86-32 chips support cpuid, so we have to check.*/
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__asm__ __volatile__(
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"pushfl\n\t"
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"pushfl\n\t"
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"popl %[a]\n\t"
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"movl %[a],%[b]\n\t"
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"xorl $0x200000,%[a]\n\t"
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"pushl %[a]\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %[a]\n\t"
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"popfl\n\t"
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:[a]"=r"(eax),[b]"=r"(ebx)
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:
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:"cc"
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);
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/*No cpuid.*/
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if(eax==ebx)return 0;
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# endif
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cpuid(0,eax,ebx,ecx,edx);
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/* l e t n I e n i u n e G*/
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if(ecx==0x6C65746E&&edx==0x49656E69&&ebx==0x756E6547||
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/* 6 8 x M T e n i u n e G*/
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ecx==0x3638784D&&edx==0x54656E69&&ebx==0x756E6547){
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int family;
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int model;
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/*Intel, Transmeta (tested with Crusoe TM5800):*/
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cpuid(1,eax,ebx,ecx,edx);
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flags=oc_parse_intel_flags(edx,ecx);
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family=(eax>>8)&0xF;
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model=(eax>>4)&0xF;
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/*The SSE unit on the Pentium M and Core Duo is much slower than the MMX
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unit, so don't use it.*/
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if(family==6&&(model==9||model==13||model==14)){
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flags&=~(OC_CPU_X86_SSE2|OC_CPU_X86_PNI);
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}
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}
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/* D M A c i t n e h t u A*/
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else if(ecx==0x444D4163&&edx==0x69746E65&&ebx==0x68747541||
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/* C S N y b e d o e G*/
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ecx==0x43534e20&&edx==0x79622065&&ebx==0x646f6547){
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/*AMD, Geode:*/
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cpuid(0x80000000,eax,ebx,ecx,edx);
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if(eax<0x80000001)flags=0;
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else{
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cpuid(0x80000001,eax,ebx,ecx,edx);
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flags=oc_parse_amd_flags(edx,ecx);
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}
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/*Also check for SSE.*/
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cpuid(1,eax,ebx,ecx,edx);
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flags|=oc_parse_intel_flags(edx,ecx);
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}
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/*Technically some VIA chips can be configured in the BIOS to return any
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string here the user wants.
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There is a special detection method that can be used to identify such
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processors, but in my opinion, if the user really wants to change it, they
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deserve what they get.*/
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/* s l u a H r u a t n e C*/
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else if(ecx==0x736C7561&&edx==0x48727561&&ebx==0x746E6543){
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/*VIA:*/
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/*I only have documentation for the C7 (Esther) and Isaiah (forthcoming)
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chips (thanks to the engineers from Centaur Technology who provided it).
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These chips support Intel-like cpuid info.
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The C3-2 (Nehemiah) cores appear to, as well.*/
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cpuid(1,eax,ebx,ecx,edx);
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flags=oc_parse_intel_flags(edx,ecx);
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if(eax>=0x80000001){
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/*The (non-Nehemiah) C3 processors support AMD-like cpuid info.
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We need to check this even if the Intel test succeeds to pick up 3DNow!
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support on these processors.
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Unlike actual AMD processors, we cannot _rely_ on this info, since
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some cores (e.g., the 693 stepping of the Nehemiah) claim to support
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this function, yet return edx=0, despite the Intel test indicating
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MMX support.
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Therefore the features detected here are strictly added to those
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detected by the Intel test.*/
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/*TODO: How about earlier chips?*/
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cpuid(0x80000001,eax,ebx,ecx,edx);
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/*Note: As of the C7, this function returns Intel-style extended feature
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flags, not AMD-style.
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Currently, this only defines bits 11, 20, and 29 (0x20100800), which
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do not conflict with any of the AMD flags we inspect.
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For the remaining bits, Intel tells us, "Do not count on their value",
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but VIA assures us that they will all be zero (at least on the C7 and
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Isaiah chips).
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In the (unlikely) event a future processor uses bits 18, 19, 30, or 31
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(0xC0C00000) for something else, we will have to add code to detect
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the model to decide when it is appropriate to inspect them.*/
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flags|=oc_parse_amd_flags(edx,ecx);
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}
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}
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else{
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/*Implement me.*/
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flags=0;
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}
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return flags;
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}
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#endif
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