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97 lines
3.3 KiB
C++
97 lines
3.3 KiB
C++
// Jolt Physics Library (https://github.com/jrouwe/JoltPhysics)
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// SPDX-FileCopyrightText: 2021 Jorrit Rouwe
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// SPDX-License-Identifier: MIT
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#pragma once
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#include <Jolt/Core/FPControlWord.h>
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JPH_NAMESPACE_BEGIN
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#ifdef JPH_FLOATING_POINT_EXCEPTIONS_ENABLED
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#if defined(JPH_CPU_WASM)
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// Not supported
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class FPExceptionsEnable { };
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class FPExceptionDisableInvalid { };
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class FPExceptionDisableDivByZero { };
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class FPExceptionDisableOverflow { };
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#elif defined(JPH_USE_SSE)
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/// Enable floating point divide by zero exception, overflow exceptions and exceptions on invalid numbers
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class FPExceptionsEnable : public FPControlWord<0, _MM_MASK_DIV_ZERO | _MM_MASK_INVALID | _MM_MASK_OVERFLOW> { };
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/// Disable invalid floating point value exceptions
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class FPExceptionDisableInvalid : public FPControlWord<_MM_MASK_INVALID, _MM_MASK_INVALID> { };
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/// Disable division by zero floating point exceptions
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class FPExceptionDisableDivByZero : public FPControlWord<_MM_MASK_DIV_ZERO, _MM_MASK_DIV_ZERO> { };
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/// Disable floating point overflow exceptions
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class FPExceptionDisableOverflow : public FPControlWord<_MM_MASK_OVERFLOW, _MM_MASK_OVERFLOW> { };
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#elif defined(JPH_CPU_ARM) && defined(JPH_COMPILER_MSVC)
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/// Enable floating point divide by zero exception, overflow exceptions and exceptions on invalid numbers
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class FPExceptionsEnable : public FPControlWord<0, _EM_INVALID | _EM_ZERODIVIDE | _EM_OVERFLOW> { };
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/// Disable invalid floating point value exceptions
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class FPExceptionDisableInvalid : public FPControlWord<_EM_INVALID, _EM_INVALID> { };
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/// Disable division by zero floating point exceptions
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class FPExceptionDisableDivByZero : public FPControlWord<_EM_ZERODIVIDE, _EM_ZERODIVIDE> { };
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/// Disable floating point overflow exceptions
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class FPExceptionDisableOverflow : public FPControlWord<_EM_OVERFLOW, _EM_OVERFLOW> { };
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#elif defined(JPH_CPU_ARM)
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/// Invalid operation exception bit
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static constexpr uint64 FP_IOE = 1 << 8;
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/// Enable divide by zero exception bit
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static constexpr uint64 FP_DZE = 1 << 9;
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/// Enable floating point overflow bit
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static constexpr uint64 FP_OFE = 1 << 10;
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/// Enable floating point divide by zero exception, overflow exceptions and exceptions on invalid numbers
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class FPExceptionsEnable : public FPControlWord<FP_IOE | FP_DZE | FP_OFE, FP_IOE | FP_DZE | FP_OFE> { };
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/// Disable invalid floating point value exceptions
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class FPExceptionDisableInvalid : public FPControlWord<0, FP_IOE> { };
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/// Disable division by zero floating point exceptions
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class FPExceptionDisableDivByZero : public FPControlWord<0, FP_DZE> { };
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/// Disable floating point overflow exceptions
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class FPExceptionDisableOverflow : public FPControlWord<0, FP_OFE> { };
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#elif defined(JPH_CPU_RISCV)
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#error "RISC-V only implements manually checking if exceptions occurred by reading the fcsr register. It doesn't generate exceptions. JPH_FLOATING_POINT_EXCEPTIONS_ENABLED must be disabled."
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#elif defined(JPH_CPU_PPC)
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#error PowerPC floating point exception handling to be implemented. JPH_FLOATING_POINT_EXCEPTIONS_ENABLED must be disabled.
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#else
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#error Unsupported CPU architecture
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#endif
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#else
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/// Dummy implementations
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class FPExceptionsEnable { };
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class FPExceptionDisableInvalid { };
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class FPExceptionDisableDivByZero { };
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class FPExceptionDisableOverflow { };
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#endif
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JPH_NAMESPACE_END
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